// 带双路输入输出端口的DUT：dio_dut.sv
module dio_dut (
    input                   clk,
    input                   rst_n,
    input       [7:0]       rx_d0,
    input                   rx_dv0,
    input       [7:0]       rx_d1,
    input                   rx_dv1,
    output reg  [7:0]       tx_d0,
    output reg              tx_en0,
    output reg  [7:0]       tx_d1,
    output reg              tx_en1
);

    always @ (posedge clk) begin
        if (!rst_n) begin
            tx_d0 <= 8'b0;
            tx_en0 <= 1'b0;
            tx_d1 <= 8'b0;
            tx_en1 <= 1'b0;
        end
        else begin
            tx_d0 <= rx_d0;
            tx_en0 <= rx_dv0;
            tx_d1 <= rx_d1;
            tx_en1 <= rx_dv1;
        end
    end

endmodule